View 8S89202BKILF_9112228.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8s89202 8s89202 rev b 7/1/15 1 ?2015 integrated device technology, inc. general description the 8s89202 is a high speed 1-to-8 differential-to-lvpecl clock divider and is part of the high performance clock solutions from idt. the 8s89202 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as sonet, 1 gigabit and 10 gigabit ethernet, and fibre channel. the internally terminated differential inputs and v ref_ac pins allow other differential signal families such as lvpecl, lvds and cml to be easily interfaced to the input with minimal use of external components. the device also has a selectable 1, 2, 4 output divider, which can allow the part to support multiple output frequencies from the same reference clock. the 8s89202 is packaged in a small 5mm x 5mm 32-pin vfqfn package which makes it ideal for use in space-constrained applications. features ? three output banks, consisting of eight lvpecl output pairs total ? inx, ninx inputs can accept the following differential input levels: lvpecl, lvds, cml ? selectable output divider values of 1, 2 and 4 ? maximum output frequency: 1.5ghz ? maximum input frequency: 3ghz ? bank skew: 6ps (typical) ? part-to-part skew: 250ps (maximum) ? additive phase jitter, rms: 0.166ps (typical) ? propagation delay: 854ps (typical) ? output rise time: 156ps (typical) ? full 2.5v5% and 3.3v10% operating supply voltage ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package pin assignment en qb0 nqb 0 qb1 nqb 1 qb2 nqb 2 v cc nqc qa3 nqa3 v cc v ee v ee v cc qc 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 25 26 27 28 29 30 31 32 12345678 nqa2 qa2 nqa1 qa1 nqa0 qa0 v cc nmr v ee divs e l_a in v t v ref_ac nin divs e l_b divs e l_c 8s89202 32-lead vfqfn 5 mm x 5mm x 0.925mm package body k package top view
low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 2 rev b 7/1/15 8s89202 data sheet block diagram in nin v ref_ac qa0 nqa0 v t qa1 nqa1 qa2 nqa2 qa3 nqa3 qc nqc 1 2 4 1 2 2 2 4 4 qb0 nqb0 qb1 nqb1 qb2 nqb2 divsel_a divsel_b divsel_c en nmr pullup pullup pullup pullup pullup r in =50 ? ?
rev b 7/1/15 3 low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8s89202 data sheet table 1. pin descriptions number name type 1, 20, 21 v ee power negative supply pins. 2 divsel_a input pullup output divider select pin. controls ou tput divider settings for bank a. see table 3 for additional information. lvcmos/lvttl interface levels. 3 in input non-inverting differentia l lvpecl clock input. r in = 50 : termination to v t. 4 v t input termination center-tap input. 5 v ref_ac output reference voltage for ac-coupled applications. 6 nin input inverting differential lvpecl clock input. r in = 50 : termination to v t. 7 divsel_b input pullup output divider select pin. controls ou tput divider settings for bank b. see table 3 for additional information. lvcmos/lvttl interface levels. 8 divsel_c input pullup output divider select pin. controls ou tput divider settings for bank c. see table 3 for additional information. lvcmos/lvttl interface levels. 9 en input pullup output enable pin. see table 3 for additional information. lvcmos/lvttl interface levels. 10, 19, 22, 31 v cc power positive supply pins. 11, 12 nqb2, qb2 output differential ou tput pair. lvpecl interfac e levels. 13, 14 nqb1, qb1 output differential ou tput pair. lvpecl interfac e levels. 15, 16 nqb0, qb0 output differential ou tput pair. lvpecl interfac e levels. 17, 18 nqc, qc output differential ou tput pair. lvpecl interfac e levels. 23, 24 nqa3, qa3 output differential ou tput pair. lvpecl interfac e levels. 25, 26 nqa2, qa2 output differential ou tput pair. lvpecl interfac e levels. 27, 28 nqa1, qa1 output differential ou tput pair. lvpecl interfac e levels. 29, 30 nqa0, qa0 output differential ou tput pair. lvpecl interfac e levels. 32 nmr input pullup master reset. see additional 3 for additional information. lvcmos/lvttl interface levels. note: pul lup refers to internal input resistor. see table 2, pin characteristics, for typical values. table 2. pin characteristics test conditions minimum typical maximum units c in input capacitance 2 pf r pullup input pullup resistor 25 k : description symbol parameter
low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 4 rev b 7/1/15 8s89202 data sheet function tables table 3. sel function table figure 1a. reset with output enabled nmr en divsel_a divsel_b divsel_c output bank a output bank b output bank c 0 n/a n/a n/a n/a 0 0 0 1 0 n/a n/a n/a 0 0 0 11000122 11111244 nin nmr en nq q nq q 1 output 2 output 4 output in nin in 1234 nmr asynchronously resets the outputs v cc /2 outputs go high simultaneously after 4 complete input clock (in) periods after nmr is de-asserted t pd /mr-q ? ? t rr nq q
rev b 7/1/15 5 low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8s89202 data sheet figure 1b. enabled timing figure 1c. disabled timing nin en nq q nq q 1 output 2 output 4 output in nin in 1234 enabled asserted v cc /2 outputs go high simultaneously after en is asserted. the number of in clock cycles after en is asserted before the outputs go high varies from 2 to 6 cycles (4 cycles shown). nq q nin en nq q nq q 1 output 2 output 4 output in nin in 1234 enabled de-asserted to disable q[0:7] outputs v cc /2 outputs go low in output sequence after en is de-asserted. the 4, 2 and 1 outputs go low in that order. the number of in clock cycles after en is de-asserted varies from 2 to 6 cycles (4 cycles shown). q nq
low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 6 rev b 7/1/15 8s89202 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functio nal operation of product at t hese conditions or any conditions beyond those listed in the dc ch aracteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current surge current 50ma 100ma input current, in, nin 50ma v t current, i vt 100ma input sink/source, i ref_ac 2ma package thermal impedance, t ja 42.7 q c/w (0 mps) storage temperature, t stg -65 q c to 150 qc dc electrical characteristics table 4a. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c table 4b. power supply dc characteristics, v cc = 3.3v 10%, v ee = 0v, t a = -40c to 85c table 4c. lvcmos/lvttl dc characteristics, v cc = 3.3v 10% or 2.5v 5%, v ee = 0v, t a = -40c to 85c item rating symbol parameter test conditio ns minimum typical maximum units v cc positive supply voltage 2.375 2.5 2.625 v i ee power supply current 117 131 ma symbol parameter test conditio ns minimum typical maximum units v cc positive supply voltage 2.97 3.3 3.63 v i ee power supply current 125 139 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v cc = 3.3v 2.2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input high current v cc = v in = 3.63v or 2.625v -125 20 a i il input low current v cc = 3.63v or 2.625v, v in = 0v -300 ua
rev b 7/1/15 7 low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8s89202 data sheet table 4d. differential dc characteristics, v cc = 3.3v 10% or 2.5v 5%, v ee = 0v, t a = -40c to 85c table 4e. lvpecl dc characteristics, v cc = 3.3v 10%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? ? ?
low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8 rev b 7/1/15 8s89202 data sheet ac electrical characteristics table 5. ac characteristics, v cc = 3.3v 10% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. ? ? ? ? ? ?
rev b 7/1/15 9 low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8s89202 data sheet additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. the noise floor of the equipment can be higher or lower than the noise floor of the device. additive phase noise is dependent on both the noise floor of the input source and measurement equipment. the additive phase jitter for this device was measured using a rohde & schwarz sma100 input source and an agilent e5052 phase noise analyzer. offset from carr ier frequency (hz) ssb phase noise dbc/hz input/output additive phase jitter, rms @ 156.25mhz (12khz to 20mhz) = 166fs typical
low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 10 rev b 7/1/15 8s89202 data sheet parameter measureme nt information 2.5v output load ac test circuit input levels single-ended & differential input swing 3.3v output load ac test circuit propagation delay output rise/fall time scope qx nqx v ee v cc 2v -0.5v 0.125v v ih cross points v in v il in nin v cc v ee v in , v out v diff_in , v diff_out differential voltage swing = 2 x single-ended v in scope qx nqx v ee v cc 2v -1.3v 0.33v t pd nqax, nqbx, nqc qax, qbx, qc nin in nqax, nqbx, nqc qax, qbx, qc 20% 80% 80% 20% t r t f v out
rev b 7/1/15 11 low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8s89202 data sheet parameter measurement in formation, continued within bank skew bank to bank skew (same divide setting) part-to-part skew bank to bank (different divide settings) qx nqx qy nqy t sk(b) qxx nqxx qxy nqxy where x = bank a, bank b or bank c t sk(pp) part 1 part 2 qx nqx qy nqy tsk(
low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 12 rev b 7/1/15 8s89202 data sheet applications information recommendations for unused input and output pins inputs: lvcmos select pins all control pins have internal pullups; additional resistance is not required but can be added for additional protection. a 1k ? ? ? ? ?? ?? ?? ? ? ?
rev b 7/1/15 13 low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8s89202 data sheet 3.3v lvpecl input with built-in 50 ? ? ? ?? ?? ?? ?? ??
low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 14 rev b 7/1/15 8s89202 data sheet termination for 2.5v lvpecl outputs figure 4a and figure 4b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ?
rev b 7/1/15 15 low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8s89202 data sheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential output is a low impedance follower output that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? ? ? ? ? ? ?
low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 16 rev b 7/1/15 8s89202 data sheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 6. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
rev b 7/1/15 17 low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8s89202 data sheet power considerations this section provides information on power dissi pation and junction temperature for the 8s89202. ? ? ? ? ? ? ? ? ? ? ? ?
low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 18 rev b 7/1/15 8s89202 data sheet 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? ? ? ? ? ? ?
rev b 7/1/15 19 low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8s89202 data sheet reliability information table 7. ? ?
low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 20 rev b 7/1/15 8s89202 data sheet 32 lead vfqfn package out line and package dimensions package outline - k suffix for 32 lead vfqfn table 9. package dimensions note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 9. reference document: jedec publication 95, mo-220 to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or s ing u l a tion n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 cid aid a re 2 method s of indic a ting pin 1 corner a t the ba ck of the vfqfn p a ck a ge: 1. type a: ch a mfer on the p a ddle (ne a r pin 1) 2. type c: mo us e b ite on the p a ddle (ne a r pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50
rev b 7/1/15 21 low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 8s89202 data sheet ordering information table 8. ordering information table 9. pin 1 orientation in tape and reel packaging part/order number marking package shipping packaging temperature 8S89202BKILF ics89202bil ?lead-free? 32 lead vfqfn tray -40 ? ? ? ? ? ?
low skew, 2:1 lvpecl mux with 1:8 fanout and internal termination 22 rev b 7/1/15 8s89202 data sheet revision history sheet rev table page description of change date b t9 8 21 21 added pin 1 orientation in tape and reel table. ordering information - added w part number. 7/1/15
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this produ ct is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

▲Up To Search▲

Price & Availability of 8S89202BKILF

	To Download 8S89202BKILF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .